module top(
           input clk,
           input rst_n,
           input key_in,

           output key_out
       );
//    松开为1，按下为0
parameter cnt_max = 32'd149999;
reg [31: 0] cnt;
wire cnt_start;
reg key_in_r;
assign cnt_start = key_in_r & ~key_in;
assign key_out = ((cnt == cnt_max) && (key_in_r == 1'b0)) ? 1'b0 : 1'b1;

always @(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			begin
				cnt <= 32'd0;
				key_in_r <= 1'b1;
			end
		else
			begin
				cnt <= (cnt == cnt_max) ? ((cnt_start) ? 32'd0 : cnt) : cnt + 1'b1;
				key_in_r <= key_in;
			end
	end
endmodule
